library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

-- Ingresa 0.ALGO y devuelve la parte entera de 160* 0.ALGO

entity FORMATO is
    port(
         clk: in std_logic;
			enable: in std_logic;
	 		Input: in std_logic_vector(15 downto 0);
	 		Output: out std_logic_vector(8 downto 0)
   	);
end FORMATO;



architecture arch of FORMATO is
begin
    process(clk)
        variable A: std_logic_vector(3 downto 0);
        variable B: std_logic_vector(3 downto 0);
        variable C: std_logic_vector(3 downto 0);
        variable carry: std_logic_vector(3 downto 0);
        variable rta: std_logic_vector(3 downto 0);
        variable numero: std_logic_vector(8 downto 0);
    begin
      if rising_edge(clk) then
			if enable='0' then
            if Input(12)='0' then
             			A:=Input(11 downto 8);
							B:=Input(7 downto 4);
							C:=Input(3 downto 0);
							for i in 3 downto 0 loop
            				if C>"0100" then
									carry(i):='1';
            					C:=C-"0101";
            				else
            					carry(i):='0';
            				end if;
            				C:=C(2 downto 0) & '0';
            				if B>"0100" then
            					rta(i):='1';
            					B:=B-"0101";
            				else
            					rta(i):='0';
            				end if;
            				B:=B(2 downto 0) & carry(i);
							end loop;
							numero:='0' & A & rta;
				else
            			numero:='0' & "10100000";
            end if;
            if Input(13)='0' then
            			output <= numero;
            else
            			output <= not(numero)+"000000001";
            end if;
			end if;
		end if;
	end process;
end arch; 
